1. Field of the Invention
The present invention relates to a method of producing a semiconductor device, and more particularly to a method of achieving isolation between elements by using a groove filled with an insulating material.
2. Description of the Prior Art
In one prior art semiconductor device of a bipolar transistor, a relatively thick field oxide film surrounds an active region (i.e., a base region and a collector contact region), as illustrated in, for example, FIG. 1 of U.S. Pat. No. 4,376,664. Such a transistor is hereinafter referred as to an oxide-surrounded transistor (OST). In the OST, a field oxide film having a thickness of from 0.4 to 2.0 .mu.m surrounds the side of the base region. Accordingly, the parasitic capacitance between the base and collector can be decreased as compared with the case where the side of the base region does not come into contact with the field oxide film. The decrease of the parasitic capacitance particularly improves transistor characteristics (e.g., switching speeds).
The above OST, however, is isolated from other elements by means of PN junction isolation. The PN junction constitutes, for example, an N-type epitaxial layer, formed on a P-type semiconductor substrate, and a P-type isolation region, extending into the substrate through the epitaxial layer and surrounding the collector region of the OST. Therefore, the PN junction capacitance between the N-type epitaxial layer and the P-type isolation region is relatively large in proportion to the junction area. Furthermore, the above OST has a collector buried layer formed in the substrate and the epitaxial layer. Since the cylindrical end portion of the buried layer exists in the substrate, the PN junction area between the collector region including the buried layer and the semiconductor substrate is larger than that betewen a collector region without the buried layer and the substrate. Therefore, the PN junction capacitance increases proportionally to the difference in area. Such a large PN junction capacitance lowers the switching speed of the bipolar transistor.